Terafab: One Terawatt of Compute Per Year
An inspiring vision, but not a realistic target.
The keynote and the gut check
When Elon announced the Terafab on March 21, my first reaction was excitement. Whatever you think of him, Musk has a way of challenging what’s deemed possible by arguing from first principles, as long as those principles don’t go against the laws of physics. SpaceX reinvented the space industry. Tesla forced the auto industry to take electric cars seriously. And here he was, saying that the current global chip industry produces about 2% of what his companies will need, which implies a roughly 50x scale-up.
AI has brought us to a (very) supply-constrained market condition, where demand is much bigger than what the world can currently supply. That makes AI infrastructure the defining industrial buildout of our time, the same way railroads and fiber were back then. The world does need a step-change in chip capacity, and watching someone with Musk’s resources and risk appetite commit Tesla, SpaceX, and xAI to attacking that bottleneck was thrilling.
Then the reality check hit me. One terawatt of compute per year. Logic, memory, packaging. Eighty percent for orbit, twenty percent for the ground.
Something in my gut didn’t seem right. I worked for years on EUV at ASML, and you learn fast that ambition has to survive contact with practical reality. As Musk himself presented, 1 TW is roughly twice the average electrical power the US economy generates. And he is pitching that in compute. Per year. To be clear, I acknowledge that landing orbital rockets reliably is hard, very hard. But that problem could be solved with a few hundred smart engineers and some serious shaking of the limited supply chain, and about 10 years of development, trial and error, and borderline bankruptcy. One terawatt per year in semiconductors is a number that touches every binding constraint in the global supply chain at once, and most of those constraints don’t give in to determination.
I wanted to make sure the gut feel was real and not biased professional reflex or skepticism.
After a brief review of what is already out there, I saw that I wasn’t the first person to look at this. Tom’s Hardware published a feasibility teardown in late March. Anastasi in Tech ran a bottom-up calculation and arrived at conclusions that overlap with the ones in this post. Igor’s Lab made the rhetorical-versus-literal point. The conclusions converge across all of these, which is itself useful. What I want to add is the view from the EUV supply chain, a multi-constraint cross-validation rather than a single-axis estimate.
To be clear, my intent here is not to argue why this cannot be done. Far from it. I always tell my teams, “don’t tell me why this cannot be done, tell me what CAN be done.” So, I’m all for going in heads first on such an enterprise. But I wanted to understand the gap between the claim and the gut feel quantitatively.
So I went and did some basic math, anchored on the Nvidia GB200 NVL72 rack and what is publicly known about it. I cross-validated across silicon volume, lithography throughput, advanced packaging, and capital expenditure. What I found is the subject of this post.
The 1 TW number is off by one to two orders of magnitude relative to what the world can offer within a decade, and that checks across every constraint independently.
Again, this is not intended as a takedown on the initiative. I admire Musk genuinely. But the number deserves to be examined, and the examination turns out to be more interesting than just “Elon is wrong” or “Elon is right.”
Why semiconductors are the wrong industry to disrupt by force
Look at the industries Musk has actually disrupted, and a pattern emerges. Auto, space, payments. Those industries had stopped trying. The auto industry in 2008 was content to make incrementally better internal combustion engines forever. The space industry before SpaceX was a cost-plus arrangement between government agencies and a handful of contractors who had no real incentive to reduce launch costs. These were industries with artificial barriers to entry, complacent incumbents, and decades of accumulated technical debt that the existing players had quietly decided was acceptable.
Musk’s playbook works remarkably well in those conditions. Vertically integrate so you don’t depend on the cartel. Reject the assumptions everyone considers immutable. Ruthlessly remove unnecessary scope and complexity. Iterate aggressively. Hire engineers willing to question what the industry calls impossible. Work hard. Push until something gives.
It worked for cars. It worked for rockets. It would probably work for several more industries. Semiconductors are not one of them.
The semiconductor industry has the opposite problem. It is the most ambitious, capital-intensive, and relentlessly optimized industrial sector on Earth. Keeping Moore’s Law alive for so long has not been a smooth ride. TSMC has driven process nodes to limits that twenty years ago would have seemed like science fiction. ASML has spent more than two decades and tens of billions of dollars on a single machine, the EUV scanner, that can image features smaller than the wavelength of the light it uses. Intel and Samsung have poured everything they can in order to stay in the game. Moore’s Law is constantly challenged because the physics is hard, not because anyone gave up. The smartest engineers on the planet never stopped trying, and the capital is deployed ever more intensively.
If you doubt this, just look at China. For more than two decades, the Chinese government has run the most aggressive industrial policy program in modern history with semiconductor sovereignty at the top of the list. Not just for economic reasons, but for national security and, honestly, survival. Made in China 2025 placed advanced semiconductors at the center of national strategy. The trade tensions made the urgency existential. China has a billion-person economy, an authoritarian state that mobilizes capital and talent in ways no Western government can conceive, and a national champion strategy that has been running for decades. It has made them the world’s manufacturing powerhouse, but they are still pretty far from bleeding-edge semiconductor sovereignty.
China is still 5 to 10 years behind on logic and likely further on lithography equipment. SMIC produced a 7nm-class chip and Huawei is advancing, but only by using DUV multipatterning workarounds because ASML is banned from selling them EUV. SMEE, the Chinese national lithography champion, is still trying to ship competitive ArF immersion DUV at scale, technology ASML perfected more than a decade ago. In December 2025 Reuters reported that China had quietly completed a prototype EUV machine in Shenzhen, expected to start chipmaking in 2028. ASML achieved a similar milestone in 2008, when a demo tool was used to produced the world’s first full-field EUV test chips, so even on this optimistic reading, China is arguably ~20 years behind on EUV alone. If a continent-scale, state-directed, hundred-billion-dollar campaign over twenty years, under existential threat, cannot close the gap, I’m not sure even the greatest entrepreneur of our times can 50x global output single-handedly. The bottleneck is the accumulated complexity of three decades of multi-disciplinary engineering, globally dependent supplier ecosystems, intellectual property, and physics.
My point is that you cannot “SpaceX your way” into state-of-the-art semiconductors. There is no underused capacity to redirect, no obvious cost to engineer out, no incumbent assumption to reject. The constraints are physical and geographical.
To his credit, Musk seems to understand this. Terafab is built around a partnership with Intel, using their 14A process at the full-scale facility. That is the right move, and, frankly, the only move. Bootstrapping a leading-edge logic process from zero would take a decade even with infinite capital, and Musk does not have a decade if Tesla and SpaceX need chips today. Intel, for its part, needs a high-volume customer for 14A to make the foundry business viable. Musk needs a process.
I told friends before the partnership was announced that this had to happen, not because I had inside information, but because no other path survived basic industry logic.
I expect the same logic to pull in two more partners shortly. Intel doesn’t do memory, and DRAM is its own multi-decade specialization, so Samsung or Micron almost has to be in the picture for HBM. Tesla already has a long-running Samsung battery cell relationship that could grease the wheels. And advanced 2.5D and 3D packaging at the scale Terafab is talking about doesn’t exist in many places, so one of the key players should come along too.
Now, no matter which partnerships, there is a difference between “from zero to something” and “from something to fifty times the entire industry.” Intel solves the first. Nothing in the announcement solves the second.
Before we look at the math on why, it’s worth giving Terafab credit for what could be potentially disruptive.
What would actually be new
Three things stand out, none of which are trivial.
The single-site recursive loop. Musk’s framing is that everything needed to ship a chip lives in one campus: design, mask making, lithography, deposition and etch, packaging, test. The pitch is iteration speed. Today, a chip company in California sends a design to TSMC in Taiwan, which sends test wafers to Malaysia for assembly, which return measurements weeks later. If a mask needs to change, the loop restarts. Compressing all of that to a single campus could collapse design-to-feedback time from months to weeks. Whether the productivity gain is 2x or 10x is debatable, but the direction is for increased agility. Vertical integration like this used to be the de facto standard before the foundry and fabless business models took over due to specialization and capital intensity. The industry separated because no single balance sheet could absorb the compounding cost of being world-class at every step, and both the foundry and fabless models worked very well. Musk has done similar verticalizations with Tesla and SpaceX, and this is the same playbook applied to a much harder target.
Cleanroom and facility design. This one I’d treat with more caution than the press has. Musk has said the industry is “getting cleanrooms wrong”. The idea is to keep the wafer enclosed in transport pods so the surrounding room doesn’t need to be clean. Modern fabs already use sealed Front Opening Unified Pods (FOUPs) to move wafers between tools, but Anastasi in Tech points out that wafers spend roughly 70% of their processing time outside the FOUP, exposed to the cleanroom environment. Every major step (lithography, etch, deposition, CMP, inspection) requires the wafer to be exposed. At 2nm, any particle landing on a circuit can ruin it. The cleanroom is doing real work. There is likely room for first-principles facility redesign around layout, gas distribution, vibration, and integration between tools. Tesla’s Giga-class plants and SpaceX’s Starbase show Musk’s organizations can rethink a factory from a blank page, but anyhow, I don't think cleanroom building is the bottleneck at all, and that any meaningful gains would probably come from layout and process flow improvements, not from declaring the cleanroom status quo obsolete.
Vertical integration of designer, fabricator, and consumer. Today, Nvidia designs, TSMC fabricates, Microsoft buys the resulting GPUs. Three companies, three sets of incentives, complexity and slowness. At Terafab, Tesla, xAI, and SpaceX would arguably be the only customers and the only owners. That eliminates the standard market-pricing layer between fabrication cost and chip economics, and adds Elon’s golden hammer advantage for same-hour decisions that would otherwise take months of articulation. For a vertically integrated AI company, that’s powerful. Google has strong verticalization, but lacks the silicon manufacturing piece. Whether it justifies running your own foundry is a separate question, but the strategic logic of internalizing the bottleneck makes sense.
These three things could make a dent on how chips are made if Terafab actually scaled. However, the reason this post exists is that none of them speak to the binding constraint of the original claim, which is volume. Recursive loops, redesigned cleanrooms, and vertical integration help with iteration speed, capital efficiency, and strategic alignment. They do not help with EUV throughput, and the 1 TW number is a volume claim.
Now we get to the math.
The math, from the ground up
The hard part of evaluating such Terafab claims in semiconductors is that the industry has so many compounding constraints that intuition breaks down quickly. A factor-of-ten error on a single independent assumption isn’t catastrophic for an order-of-magnitude estimate. But if the same error stacks across multiple compounding factors, the takeaways become meaningless. To mitigate that risk, here we will estimate independently along four reasonably orthogonal axes and see if they triangulate.
As mentioned, I’m going to anchor the calculations on the Nvidia GB200 NVL72 rack and what is publicly known about it. We’ll address Rubin and post-Rubin architectures in the next section.
The analysis runs across four axes: Silicon volume, lithography throughput, advanced packaging, and capital expenditure.
Power generation is set aside, because Musk has said most of the compute is destined for orbit anyways, and we’ll take that framing at face value for this exercise.
Silicon volume
The GB200 NVL72 rack draws roughly 120 kW and contains 72 Blackwell GPUs, putting AI compute density at about 1.67 kW per GPU at the rack level. To deliver 1 TW of compute you'd need ~8.3 million racks. At 72 GPUs per rack, that’s 600 million Blackwell-class GPUs per year. And here we are assuming GPU racks only, which are the most power hungry. In reality, data centers hold a mix of rack types. Nvidia’s new Vera Rubin platform consists of five purpose-built rack-scale systems, including dedicated CPU racks and storage racks. So by assuming an all-GPU rack mix, we are being generous to Musk's number.
For context, Nvidia has reportedly shipped ~3 million Blackwell GPUs packages in 2025. So 600 million GPUs per year for Terafab is about 200x Nvidia’s 2025's output. That’s the first reality hit.
A B200 package contains two reticle-limited chiplets, each around 800 square millimeters, fabricated on TSMC’s 4NP process. With and edge loss of 3mm, you get 69 dies per wafer. At a moderate yield of 70%, you get roughly 25 finished GPU packages per 300mm wafer. At that ratio, 600 million GPUs require about 24 million wafers of leading-edge logic silicon.
Dropping the specificity of 4NP, lets take TSMC’s total leading-edge capacity across N3, N4, and N5, and assume that is about 3.5 to 4 million wafers per year at the end of 2025. The 1 TW target consumes about 5 to 6 years of TSMC’s entire leading-edge output for the GPU silicon alone. And that ignores the fact that an AI rack also contains a large amount of CPU silicon and networking, all of which compete for the same leading-edge wafers. The realistic logic wafer requirement is likely closer to 25 to 30 million wafers per year, or roughly 7 to 8 years of TSMC’s leading-edge output.
TSMC also doesn’t do HBM, which is its own story. Each B200 package carries eight stacks of HBM3E. Six hundred million GPUs require 4.8 billion HBM stacks per year. Combined HBM stack output across the three HBM producers (SK Hynix, Samsung, Micron) is expected around 300 to 400 million stacks per year in 2026, with Samsung alone targeting 250,000 wafers per month of HBM-dedicated DRAM by end of year and a 47 percent capacity increase. So Terafab alone would need roughly 12 to 15 times current global HBM stack output.
Takeaway: Terafab would have to ramp the equivalent of 6-8x full TSMC’s leading edge output just for the logic portion, and then separately something like 13x the HBM output of SK Hynix, Micron and Samsung combined.
Lithography throughput
In practical terms, virtually all advanced chips manufacturing require some level of EUV. So, a critical scalability question to be made is: How many EUV wafer-layers per hour are needed for the Terafab project, versus current supply reality?
Here’s the brief context. EUV stands for extreme ultraviolet. It’s a lithography technique that uses light at 13.5 nanometers to print circuit patterns onto silicon. At modern leading and bleeding-edge nodes, every layer below about 7 nanometers practically requires it. ASML in the Netherlands is the only company on Earth that makes EUV scanners. The current production model, the NXE:3800E, weighs around 180 metric tons, costs about $180 million, contains roughly 100,000 parts, and takes months to be produced, installed and qualified at a customer. Through the end of 2025, there were approximately 330 high volume manufacturing (HVM) EUV scanners globally (NXE:3400B and later), deployed primarily across TSMC, Samsung, Intel, SK Hynix, and Micron. ASML delivered 48 EUV systems in 2025, and is guiding 60 in 2026, and 80 in 2027.
This is unprecedented scaling for ASML, to increase the EUV systems output by 66% in only two years, considering the company has for long been squeezing every drop of juice from the supply chain.
A modern EUV scanner is the most complex machine humanity has ever mass-produced, and the supply chain that feeds it is itself the biggest constraint behind ASML’s ramp. Carl Zeiss SMT in Oberkochen, Germany, makes the EUV optics. These are mirrors instead of lenses, polished to a flatness that, if you scaled one up to the size of Germany, would have its largest bump under one millimeter. The production process depends on a small pool of optical engineers and mirror specialists trained over multiple years at Zeiss. Trumpf in Ditzingen, also Germany, makes the high-power CO2 lasers that drive the light source. Cymer, a San Diego company acquired by ASML in 2013, designs the laser-produced plasma source where a stream of molten tin droplets is struck twice per droplet by the CO2 laser, at 50,000 times per second, to produce the 13.5 nm photons. VDL in Eindhoven, Netherlands, supplies several of the high-precision mechatronic modules. Jenoptik and a long tail of smaller European optics, vacuum, and precision-stage companies fill out the rest. ASML’s vertical integration of Berliner Glas in 2020 was itself a sign of how constrained this supply chain is. The Veldhoven factory floor has a finite footprint, and you cannot double EUV output by hiring more people the way you might with software. Every machine assembly is the result of mostly manual work done by highly trained personnel.
Now the throughput calculation. The NXE:3800E has a published throughput of 220 wafers per hour at the standard 30 mJ/cm² dose. Real-world fab operations achieve about 85 percent uptime once you account for planned maintenance, mask changes, light source service intervals, calibration cycles, and unplanned downtime. A leading-edge logic node like TSMC’s 4NP family (the one which B200 is produced with) uses about 15 EUV layers per wafer, where each layer represents one pass through the scanner. Some of these are double-patterning passes that effectively cost two layer-equivalents each. For Intel 14A, which is the proclaimed Terafab process, the EUV layer count is likely higher, possibly 20 to 25. But for an order-of-magnitude conservative estimate, lets use 15 Low-NA-equivalent exposures at 220 wph.
Multiplying it out, one EUV scanner processes:
220 exposures/hour × 24 hours × 365 days × 0.85 uptime ≈ 1.64 million exposures per year
To produce the GPU silicon alone (B200-equivalent), as presented in the last section, we need 28 million wafers. If each requires 15 EUV layers, we need 420 million wafer-layers annually. That’s about 256 NXE:3800E scanners at full steam, dedicated exclusively to Terafab.
Pause here. As of today, the entire global HVM installed base of EUV scanners is approximately 330 machines. Terafab alone, on the GPU silicon line alone, would need about 250 EUV scanners. That's roughly two thirds of all machines at TSMC, Samsung, Intel, SK Hynix, Micron, etc. combined.
And remember that this is for GPUs only. Once you include the CPUs, HBM and networking silicon, the real EUV layer demand climbs to something like 700 million wafer-layers per year or more. That’s closer to 430 scanners.
Let’s say you accept that and decide to build more. ASML produces 60 EUV systems per year today, plans to scale to 80 by 2027. The longer-term throughput ambition is around 330 wafers per hour by 2030 using a 1,000W source, which would lift effective per-machine output. Even on the most optimistic ramp, building 430 net-new machines for Terafab, exclusively for Terafab, would consume 4-6 years of ASML’s entire global production. That assumes every other customer accepts a complete pause in their leading-edge expansion, which obviously they will not. ASML’s revenue base is concentrated in TSMC, Samsung, Intel, SK Hynix, and Micron, of which Taiwan alone typically accounts for 30 to 45 percent of system sales. I cannot imagine a world where ASML burns those relationships to allocate any meaningful output to a newcomer, however well-capitalized and well-connected.
But why can’t ASML just scale up faster? Because the constraints are upstream of Veldhoven. Every doubling of EUV output requires Zeiss to roughly double mirror output, which depends on hand-finished optical processes and a small population of master polishers. It requires Trumpf to double laser output. It requires Cymer to double tin-droplet source production. It requires VDL to double mechatronic stage output. Each of these companies is itself already running flat out. For years I worked on the image sensors that go inside the EUV systems, and I watched the company push every lever it had to ramp output. The factory operations team would tear into engineering whenever anything we did slowed down production. The constraints are real, and they don’t yield to capital alone.
So the lithography constraint stands. To deliver 1 TW of compute per year on Blackwell-class economics, Terafab needs more EUV machines than exist on Earth, and the world’s only EUV manufacturer can build them at a rate that means the fleet would not be installed for at least a decade, even under impossible assumptions about market priority.
And there’s a more immediate question. When does Terafab get its first EUV machine? ASML’s order book is fully committed into 2027 and beyond. Unless Intel hands over an allocation as part of the 14A partnership, Terafab is queuing behind every other leading-edge program on the planet.
This is what I mean when I say the analysis goes from constrained to physically impossible.
Advanced packaging
A modern AI accelerator is not just a logic die. The B200 package contains two reticle-limited compute dies, eight stacks of HBM3E memory, and a silicon interposer that ties them together with thousands of micro-bump connections. That entire assembly is what TSMC calls CoWoS, chip-on-wafer-on-substrate, and it is an enormous bottleneck of the AI hardware industry. Nvidia, TSMC, and AMD have all said as much on the record. Nvidia management has called CoWoS oversubscribed through at least mid-2026. TSMC’s CEO has said capacity is sold out. The constraint isn’t speculative.
TSMC’s total CoWoS capacity in 2026, after multiple aggressive expansions, is climbing toward 130,000 wafers per month by year-end, or roughly 1.5 million wafers per year. Each CoWoS wafer yields on the order of ten finished AI accelerator packages, depending on die size and HBM count. To deliver 600 million Blackwell-class GPUs per year, Terafab would need roughly 60 million CoWoS-equivalent wafers, or about 40 times TSMC’s current full output. Building that capacity isn’t possible on TSMC’s current expansion rate, and TSMC is essentially the only CoWoS supplier in the world. Intel’s EMIB and Foveros are picking up second-tier traffic, and ASE is developing CoWoP as a TSMC alternative, but neither operates at the scale that matters here. Would Terafab design a chip that doesn’t need 2.5D advanced packaging? That would mean designing around HBM, which the next section says is even harder.
One can argue about the precise multiplier, but not that packaging is solved when silicon and lithography are solved. It is its own independent constraint, with its own supplier ecosystem, its own multi-year ramp times, and its own physics around interposer yield, micro-bump density, and thermal dissipation in 3D-stacked memory.
The packaging constraint independently says the math doesn’t close.
Capital expenditure
The fourth constraint is money. There are two numbers worth circulating.
Bernstein estimates that building the chip-capacity portion of 1 TW of compute would cost between $5 trillion and $13 trillion in capital expenditure. These numbers cover the fabs themselves including the lithography tools, etch and deposition, packaging lines, and the buildings around them. They do not cover the data centers, the power generation, the transformers, the cooling infrastructure, or the orbital launch costs Musk would need on top.
For the data center half of the stack, Crusoe’s CEO Chase Lochmiller, in a Stanford lecture, broke down the full upfront capex for AI data centers at about $59 million per megawatt all-in, including the data center build and power plant ($19M/MW), the GPUs ($30M/MW), and other AI infrastructure ($10M/MW). At that ratio, 1 TW of data center capacity is roughly $59 trillion, or more than half of world GDP for a single year of buildout. The fab portion is on top of that. Unless Elon can magically reduce the per-GW data center cost in orbit, the total capital requirement is obviously unattainable for any single company. Getting payloads to orbit isn’t cheap either, in case the argument was going to be “this all gets easier in space.”
Raising that level of capital is completely unprecedented. Even amortized over 100 years, $5 trillion divided by 100 is still $50 billion per year, which is close to what each individual hyperscaler is spending on AI capex this year. The 1 TW vision financed at a credible pace is asking the entire hyperscaler capex base to be redirected to a single project for a century. In my view, only a humanity-level existential threat, like aliens invading or Skynet really coming for us, would create the incentives for an investment of this magnitude.
Triangulation
Four independent evaluations: Silicon volume says the equivalent of six to eight years of TSMC’s leading-edge output. Ldðithography says more EUV machines than currently exist on Earth, with build-out times that consume multiple years of ASML’s total production. Packaging says 30 to 40 times current CoWoS capacity, plus 12 to 15 times global HBM. Capital says investment levels comparable to the combined GDP of the world’s largest economies.
The 1 TW number does not survive contact with any of the binding constraints in the real world. The pattern tells you that the number was chosen first for rhetorical reasons, before anyone did a feasibility study.
What if I’m wrong?
What arguments could push these numbers in Terafab’s favor? Even if Terafab doesn’t reach 1 TW, directionally how disruptive could this endeavor be to the industry?
New chip architectures. A fair pushback to a Blackwell-anchored calculation is that future architectures will have higher compute density, so you need fewer chips per gigawatt. This is true and important. Looking at Nvidia’s last few generations, each at the best low-precision format the chip natively supports (which is the only fair way to compare across generations when the precision regime keeps changing):
H100 in 2022: 700W, 989 TFLOPS dense FP16, ~1.4 TFLOPS/W
B200 in 2024: 1,200W, 9,000 TFLOPS dense FP4, ~7.5 TFLOPS/W
Rubin R100 in late 2026: 1,800W to 2,300W, 50,000 TFLOPS NVFP4 inference, ~22 to 28 TFLOPS/W
That’s roughly 15x improvement in compute-per-watt over four years, with about half coming from the precision regime shift (FP16 to FP4) and the rest from architecture, process, and packaging. If you project another 10x to 30x improvement in compute per watt over the next decade through architecture, packaging, and continued precision compression, then 1 TW of “compute” becomes equivalent to maybe 30 to 100 GW of silicon area at current efficiency. That moves the EUV math from 430 scanners down to 14 to 43. That is no longer “physically impossible.” It is “extremely demanding,” roughly equivalent to two to four years of ASML’s projected total output dedicated to one project. The catch is that you’re also redefining what “1 TW of compute” means. The metric becomes a function of precision and architecture, which is exactly Igor’s Lab’s point about the 1 TW figure being a rhetorical metric rather than an industrial one.
The power-density lens. There’s another way to read the 1 TW number. Musk didn’t say “today’s compute.” He said 1 TW of compute, period. A natural reading is that 1 TW means 1 TW of AI silicon installed, doing whatever the year’s best architecture can do at that power budget. That framing changes the rack math, not the wafer math. The GB200 NVL72 draws 120 kW per rack. The upcoming Rubin Ultra NVL576 “Kyber” rack is targeted at 600 kW. One generation past that could push to roughly 1.2 MW per rack. At 600 kW per rack, 1 TW of installed AI silicon is 1.67 million racks, not 8.3 million. One more doubling brings it to about 800,000 racks. The rack count gets manageable. But silicon per rack scales up at the same time. Rubin Ultra packages each carry four compute dies plus eight HBM4E stacks, versus two compute dies and eight HBM3E stacks on Blackwell. The wafer-area requirement doesn’t drop nearly as fast as the rack count does, because each watt of rack power buys more transistor density without a proportional drop in silicon area. The power-density lens shrinks the rack and floor-space problem. It does not shrink the silicon-area, lithography, or packaging problem nearly as much. The bottleneck stays in the fab.
Wafer-scale architectures. Companies like Cerebras take a different path, building wafer-scale chips that pack 900,000 cores onto a single dinner-plate-sized piece of silicon. Wafer-scale eliminates a lot of the packaging overhead and improves compute-per-watt by reducing interconnect losses. If Terafab adopted a wafer-scale architecture instead of GB200-style packaged dies, you could realistically cut the silicon volume requirement by another 3 to 5x. None of this gets you to 50x for free, but stacking a 20-30x architectural gain and a 3-5x packaging gain over a decade gets you to roughly 100x reduction in silicon volume, which closes a meaningful chunk of the original gap, if you also accept that you’re optimizing the metric to flatter the headline.
The timeline objection. Musk gave no timeline. What if the 1 TW figure is implicitly a ten-year goal, or a twenty-year goal? The math gets less violent as the timeframe stretches, particularly if you extrapolate the exponential improvements above. Musk has a strong track record of stating goals that are clearly multi-decade. SpaceX was founded in 2002 around the goal of a multi-planetary civilization, with Mars as the explicit endpoint. Twenty-four years later, no human has gone to the Moon under SpaceX, let alone Mars, but the company has revolutionized launch economics, made reuse routine, and built Starlink. The vision pulled the company forward even when it didn’t materialize on schedule.
A 1 TW Terafab interpreted as a 25-year aspiration is a different conversation than a 1 TW Terafab interpreted as something that gets close in the 2030s. The longer horizon is where Musk’s track record actually argues for taking the number seriously. The shorter horizon is where the supply chain math says no.
How to read a Musk number
Since SpaceX was founded in 2002, Musk has been actively and vocally investing in colonizing Mars. Read literally, that statement was absurd at the time, particularly when space technology was thought to be all NASA could deliver on a stagnant industry. While SpaceX hasn’t even gone to the Moon yet, let alone Mars, no one can argue against the fact that they’ve revolutionized launch economics, made rocket reusability routine, and built the biggest and most lucrative satellite constellation in space, all of which are putting SpaceX IPO talks above a $2 trillion valuation. All that, partly because of the gravitational pull of an absurd vision. The vision attracts the best engineers in the world. The track record in delivering pulls in capital. It justifies risk-taking that incremental goals would not. And on the path toward the impossible target, real businesses get monetized that fund the next stage. It’s a truly powerful force for progress.
Musk is exceptionally good at this. He sets a number that no honest engineer would defend, and he uses the gap between that number and reality as fuel.
The 1 TW figure may be doing the same work. The number is functional rather than literal. It pulls talent, justifies capital that wouldn’t otherwise show up, and signals to an industry he has decided needs disruption that someone with serious resources is willing to compete. Criticizing it for not being literally true is missing the point of why he will pursue it.
The criticism still matters though. If the industry treats the 1 TW number as a literal forecast with no realistic intermediate milestones and reasonable masterplan, it won’t get credit when partial wins materialize, and it won’t get held to account when promises slip.
What’s actually possible?
If 1 TW per year is the rhetorical ceiling, what does a credible Terafab look like?
The most ambitious realistic plan I can construct, given the constraints, is something like 50 to 100 GW per year buildout over a decade, anchored on Intel succeeding in their bleeding-edge nodes, with vertical integration across logic, packaging, and HBM. That’s roughly 5 to 10 percent of Musk’s stated number. It would also be the largest single semiconductor capacity expansion in human history. It would consume on the order of 80 to 160 EUV scanners over the build, equivalent to two to four years of ASML’s projected output dedicated to one project. It would cost several trillion. And it would still be transformative for AI infrastructure, just not in the way Musk described it.
That is the version of Terafab worth taking seriously. The 1 TW version is a vision, a source of inspiration. The 50 to 100 GW version could become a 5-to-10-year plan.
The number is the number
Having become the world’s wealthiest self-made entrepreneur and the most consequential industrialist of our era, Musk has earned the right to set audacious visions. Tesla and SpaceX exist because he was willing to commit to numbers that better-informed people called lunacy, and he was right enough times to cause technological disruption a number of times. But the calibration cuts both ways. Some of his numbers came true, but very late and with revisions. Full self-driving was promised by 2018 and is still not fully autonomous in 2026. The Tesla Semi was supposed to be in volume production by 2020. The Cybertruck slipped by years. The 100 GWh of in-house battery cell production targeted for 2022 still hasn’t happened at that scale. And some did not arrive at all. SolarCity, the rocket-from-anywhere-to-anywhere trip, the tunnel network under Los Angeles, the million-person Mars city, the Hyperloop. The track record is mixed precisely because the vision-setting machinery is calibrated for inspiration, not for forecasting.
The 1 TW figure belongs in the inspiration category. Treat it that way, and it is the most useful provocation the AI infrastructure industry has had in years. Treat it as a literal capacity number, and you are setting yourself up for the same flavor of disappointment that anyone who bet on a 2020 Hyperloop service is currently feeling.
But EUV throughput doesn’t care about vision. Quantum mechanics doesn’t read keynotes. The number is the number, and the number says 1 TW per year is a metaphor.